C_in(carryInAdder2)) įor some reason, I keep getting the following outputs: Wire adder1C_out, carryInAdder2, adder2C_out īinary_adder adder1 (.Sum(Z). I am trying to write a BCD Adder in Verilog using two Full Adders with some logic in between for conversion to BCD when needed. I'm new to Verilog and basically trying to teach myself a Digital Logic Design module for university.
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